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ISQED
2006
IEEE
142views Hardware» more  ISQED 2006»
13 years 11 months ago
Constructing Current-Based Gate Models Based on Existing Timing Library
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
Andrew B. Kahng, Bao Liu, Xu Xu
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Analysis and optimization of gate leakage current of power gating circuits
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
Hyung-Ock Kim, Youngsoo Shin
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
14 years 1 months ago
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Saraju P. Mohanty, Elias Kougianos
ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
13 years 10 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun