59 search results - page 11 / 12 » Hierarchical Test Generation with Built-In Fault Diagnosis |
DAC
2000
ACM
14 years 7 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
ET
2000
13 years 5 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
ITC
1997
IEEE
13 years 10 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
KI
2009
Springer
14 years 16 days ago
2009
Springer
Today’s complex production systems allow to simultaneously build different products following individual production plans. Such plans may fail due to component faults or unfores...
ITC
2002
IEEE
13 years 11 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...