8 search results - page 1 / 2 » High-Level Delay Estimation for Technology-Independent Logic... |
ICCAD
1990
IEEE
13 years 9 months ago
1990
IEEE
DAC
1997
ACM
13 years 9 months ago
1997
ACM
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
FPGA
2008
ACM
13 years 7 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...