38 search results - page 2 / 8 » High-level test synthesis for delay fault testability |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
INTEGRATION
2006
13 years 5 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...