12 search results - page 2 / 3 » High-performance ULSI: the real limiter to interconnect scal... |
DAC
1998
ACM
14 years 6 months ago
1998
ACM
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is ...
GLVLSI
2000
IEEE
13 years 10 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
DFT
2008
IEEE
13 years 12 months ago
2008
IEEE
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
EWSN
2010
Springer
13 years 8 months ago
2010
Springer
Experimentally driven research for wireless sensor networks is invaluable to provide benchmarking and comparison of new ideas. An increasingly common tool in support of this is a t...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...