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» High-performance routing at the nanometer scale
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GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
HPCA
2009
IEEE
14 years 17 days ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
USENIX
2001
13 years 7 months ago
Flexible Control of Parallelism in a Multiprocessor PC Router
SMP Click is a software router that provides both flexibility and high performance on stock multiprocessor PC hardware. It achieves high performance using device, buffer, and queu...
Benjie Chen, Robert Morris
DAC
2005
ACM
14 years 6 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
CLUSTER
2006
IEEE
13 years 12 months ago
A Simple Synchronous Distributed-Memory Algorithm for the HPCC RandomAccess Benchmark
The RandomAccess benchmark as defined by the High Performance Computing Challenge (HPCC) tests the speed at which a machine can update the elements of a table spread across globa...
Steven J. Plimpton, Ron Brightwell, Courtenay Vaug...