16 search results - page 1 / 4 » Implementation of Concurrent Checking Circuits by Independen... |
DFT
2005
IEEE
14 years 4 months ago
2005
IEEE
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
DAC
2000
ACM
14 years 11 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
ITC
1999
IEEE
14 years 3 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
ASYNC
2002
IEEE
14 years 3 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...