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» Improve Chip Pin Performance Using Optical Interconnects
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ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
13 years 11 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
TPHOL
2009
IEEE
13 years 12 months ago
Formal Analysis of Optical Waveguides in HOL
Optical systems are becoming increasingly important as they tend to resolve many bottlenecks in the present age communications and electronics. Some common examples include their u...
Osman Hasan, Sanaz Khan Afshar, Sofiène Tah...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
13 years 10 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 3 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
13 years 12 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...