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» Improving the reliability of on-chip data caches under proce...
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ICCD
2007
IEEE
180views Hardware» more  ICCD 2007»
14 years 1 months ago
Improving the reliability of on-chip data caches under process variations
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lie...
TVLSI
2008
150views more  TVLSI 2008»
13 years 4 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
13 years 11 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
ASPDAC
2008
ACM
174views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
ASPLOS
1992
ACM
13 years 8 months ago
Parity Declustering for Continuous Operation in Redundant Disk Arrays
We describe and evaluate a strategy for declustering the parity encoding in a redundant disk array. This declustered parity organization balances cost against data reliability and...
Mark Holland, Garth A. Gibson