Sciweavers

Share
ISVLSI
2007
IEEE

Designing Memory Subsystems Resilient to Process Variations

9 years 6 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte-Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a cache subsystem under both typical and worst-case conditions. The distribution of a cache critical-path-delay in the typical scenario was determined by performing Monte-Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISVLSI
Authors Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
Comments (0)
books