8 search results - page 1 / 2 » Improving the testability and reliability of sequential circ... |
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...