21 search results - page 1 / 5 » Incremental physical resynthesis for timing optimization |
FPGA
2004
ACM
13 years 8 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
TCAD
2008
13 years 4 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
INTEGRATION
2006
13 years 4 months ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...