71 search results - page 2 / 15 » Integrating Path and Timing Analysis Using Instruction-Level... |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...