384 search results - page 1 / 77 » Latch Modeling for Statistical Timing Analysis |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
TCAD
2008
13 years 4 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...