5 search results - page 1 / 1 » Layout-Aware Transition-Delay Fault Pattern Generation with ... |
JOLPE
2008
13 years 6 months ago
2008
DATE
2008
IEEE
14 years 18 days ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
VTS
2008
IEEE
14 years 16 days ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
VTS
2007
IEEE
14 years 12 days ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
TCAD
2002
13 years 5 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...