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    DAC
    2005
    ACM
    96views Computer Architecture» more  DAC 2005»
    Leakage power optimization with dual-Vth library in high-level synthesis
    14 years 5 months ago
    Leakage power optimization with dual-Vth library in high-level synthesis
    Download  www.ece.northwestern.edu
    Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
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    DAC
    2008
    ACM
    162views Computer Architecture» more  DAC 2008»
    Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
    13 years 6 months ago
    Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
    Download  users.eecs.northwestern.edu
    Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
    Min Ni, Seda Ogrenci Memik
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    ISLPED
    2005
    ACM
    111views Hardware» more  ISLPED 2005»
    Peak temperature control and leakage reduction during binding in high level synthesis
    13 years 10 months ago
    Peak temperature control and leakage reduction during binding in high level synthesis
    Download  www.eecs.northwestern.edu
    Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
    Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
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    VLSID
    2009
    IEEE
    155views VLSI» more  VLSID 2009»
    Unified Challenges in Nano-CMOS High-Level Synthesis
    14 years 5 months ago
    Unified Challenges in Nano-CMOS High-Level Synthesis
    Download  www.cse.unt.edu
    : The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
    Saraju P. Mohanty
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    ISQED
    2008
    IEEE
    153views Hardware» more  ISQED 2008»
    ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
    13 years 11 months ago
    ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
    Download  www.cse.unt.edu
    In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
    Saraju P. Mohanty
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