60 search results - page 2 / 12 » Memory Estimation for High Level Synthesis |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
DAC
1992
ACM
13 years 9 months ago
1992
ACM
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
FPL
2009
Springer
13 years 8 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...