36 search results - page 2 / 8 » Memory bank aware dynamic loop scheduling |
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
DSD
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
MICRO
1995
IEEE
14 years 28 days ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
CORR
2010
Springer
13 years 6 months ago
2010
Springer
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...