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ET
2002
85views more  ET 2002»
13 years 5 months ago
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Mehrdad Nourani, Amir Attarha
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
13 years 9 months ago
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
13 years 9 months ago
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerf...
Michele Borgatti, Andrea Capello, Umberto Rossi, J...
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
TCAD
2002
73views more  TCAD 2002»
13 years 4 months ago
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
Vikram Iyengar, Krishnendu Chakrabarty