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    ET
    2002
    85views more  ET 2002»
    Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
    13 years 6 months ago
    Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
    Download  www.utdallas.edu
    As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
    Mehrdad Nourani, Amir Attarha
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    ASPDAC
    2007
    ACM
    109views Hardware» more  ASPDAC 2007»
    On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
    13 years 10 months ago
    On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
    Download  vda.ee.nctu.edu.tw
    Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
    Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
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    DATE
    2004
    IEEE
    136views Hardware» more  DATE 2004»
    An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
    13 years 10 months ago
    An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
    Download  hal.archives-ouvertes.fr
    Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerf...
    Michele Borgatti, Andrea Capello, Umberto Rossi, J...
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    ASPDAC
    2007
    ACM
    101views Hardware» more  ASPDAC 2007»
    Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
    13 years 10 months ago
    Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
    Download  www.cecs.uci.edu
    Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
    Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
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    TCAD
    2002
    73views more  TCAD 2002»
    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
    13 years 5 months ago
    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
    Download  people.ee.duke.edu
    Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
    Vikram Iyengar, Krishnendu Chakrabarty
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