71 search results - page 1 / 15 » Mining IC test data to optimize VLSI testing |
KDD
2000
ACM
13 years 8 months ago
2000
ACM
We describe an application of data mining and decision analysis to the problem of die-level functional test in integrated circuit manufacturing. Integrated circuits are fabricated...
VLSI
2005
Springer
13 years 10 months ago
2005
Springer
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
ESA
2008
Springer
13 years 6 months ago
2008
Springer
Abstract. A level graph is a directed acyclic graph with a level assignment for each node. Such graphs play a prominent role in graph drawing. They express strict dependencies and ...