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GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
13 years 5 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
13 years 10 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
13 years 9 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
MJ
2007
87views more  MJ 2007»
13 years 4 months ago
Using SAT-based techniques in power estimation
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wi...
Assim Sagahyroon, Fadi A. Aloul