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ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
13 years 11 months ago
Multi-layer global routing considering via and wire capacities
Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
TCAD
2010
112views more  TCAD 2010»
12 years 11 months ago
Multilayer Global Routing With Via and Wire Capacity Considerations
Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a sim...
Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 1 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
13 years 10 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra