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MICRO
2008
IEEE
142views Hardware» more  MICRO 2008»
13 years 11 months ago
NBTI tolerant microarchitecture design in the presence of process variation
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
Xin Fu, Tao Li, José A. B. Fortes
HPCA
2009
IEEE
13 years 11 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
TCAD
2008
100views more  TCAD 2008»
13 years 4 months ago
Robust Clock Tree Routing in the Presence of Process Variations
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
13 years 11 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
13 years 8 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh