5 search results - page 1 / 1 » Net and Pin Distribution for 3D Package Global Routing |
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper, we study the net and pin distribution problem for global routing targeting three dimensional packaging layout via System-on-Package (SOP). The routing environment f...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in...
TCAD
2002
13 years 5 months ago
2002
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
ICCAD
2008
IEEE
13 years 11 months ago
2008
IEEE
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...