27 search results - page 2 / 6 » On Optimizing Scan Testing Power and Routing Cost in Scan Ch... |
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
ISQED
2010
IEEE
13 years 10 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
DFT
2005
IEEE
13 years 6 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...