123 search results - page 1 / 25 » On Statistical Timing Analysis with Inter- and Intra-Die Var... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
TVLSI
2008
13 years 4 months ago
2008
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...