34 search results - page 3 / 7 » On test conditions for the detection of open defects |
ITC
1989
IEEE
13 years 9 months ago
1989
IEEE
- The electrical effects of CMOS IC physical defects that caused stuck-openfaults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient re...
PADL
2010
Springer
14 years 2 months ago
2010
Springer
Abstract. We address the problem of detecting some commonly occurring kinds of race conditions in Erlang programs using static analysis. Our analysis is completely automatic, fast ...
DATE
2007
IEEE
14 years 3 days ago
2007
IEEE
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
ITC
1996
IEEE
13 years 10 months ago
1996
IEEE
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...