Sciweavers

9 search results - page 1 / 2
» Optimized self-tuning for circuit aging
Sort
View
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
13 years 10 months ago
Optimized self-tuning for circuit aging
We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduc...
Evelyn Mintarno, Joelle Skaf, Rui Zheng, Jyothi Ve...
DAC
2009
ACM
14 years 6 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
14 years 6 days ago
Gate replacement techniques for simultaneous leakage and aging optimization
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao,...
MICRO
2008
IEEE
88views Hardware» more  MICRO 2008»
13 years 12 months ago
Facelift: Hiding and slowing down aging in multicores
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
Abhishek Tiwari, Josep Torrellas
ATS
2009
IEEE
92views Hardware» more  ATS 2009»
13 years 3 months ago
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
Song Jin, Yinhe Han, Lei Zhang 0008, Huawei Li, Xi...