8 search results - page 1 / 2 » PWAM signalling scheme for high speed serial link transceive... |
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a new signaling scheme called PWAM (pulse width and amplitude modulation) to obtain the optimum combination of bandwidth and performance of the serial link tra...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ET
2002
13 years 4 months ago
2002
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
TVLSI
2010
12 years 11 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...