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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 9 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
13 years 9 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
COR
2008
164views more  COR 2008»
13 years 5 months ago
Observations in using parallel and sequential evolutionary algorithms for automatic software testing
In this paper we analyze the application of parallel and sequential evolutionary algorithms (EAs) to the automatic test data generation problem. The problem consists of automatica...
Enrique Alba, J. Francisco Chicano
VTS
1996
IEEE
126views Hardware» more  VTS 1996»
13 years 9 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
EVOW
1999
Springer
13 years 9 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...