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IPPS
2007
IEEE
13 years 11 months ago
Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems
When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and de...
Florian Dittmann, Marcelo Götz, Achim Rettber...
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
13 years 10 months ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
VLSISP
2008
123views more  VLSISP 2008»
13 years 5 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
DELTA
2008
IEEE
13 years 11 months ago
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
Hans G. Kerkhoff, Jarkko J. M. Huijts
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
13 years 9 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...