29 search results - page 1 / 6 » Path delay test compaction with process variation tolerance |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
IOLTS
2005
IEEE
13 years 10 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...