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DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 8 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
VTS
2000
IEEE
167views Hardware» more  VTS 2000»
13 years 9 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
ITC
2003
IEEE
124views Hardware» more  ITC 2003»
13 years 9 months ago
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ
Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under...
Chris Schuermyer, Brady Benware, Kevin Cota, Rober...
TCAD
2008
114views more  TCAD 2008»
13 years 4 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
13 years 11 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...