173 search results - page 2 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
ASYNC
2005
IEEE
13 years 11 months ago
2005
IEEE
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
TIM
2010
13 years 4 days ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...