318 search results - page 2 / 64 » Power minimization for dynamic PLAs |
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
EUC
2008
Springer
13 years 7 months ago
2008
Springer
This paper studies the scheduling and assignment problem that minimizes the total energy including both dynamic and leakage energy for applications with loops on multi-voltage, mul...
CEC
2005
IEEE
13 years 11 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
TVLSI
2008
13 years 5 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
VLSID
2007
IEEE
14 years 6 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...