17 search results - page 2 / 4 » Redundant-via enhanced maze routing for yield improvement |
SLIP
2005
ACM
13 years 11 months ago
2005
ACM
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
CDES
2006
13 years 6 months ago
2006
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
- In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhan...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
PIMRC
2010
IEEE
13 years 3 months ago
2010
IEEE
Delay Tolerant networks (DTNs) are one type of wireless networks where the number of nodes per unit area is small and hence the connectivity between the nodes is intermittent. In t...