76 search results - page 2 / 16 » Register placement for low power clock network |
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ICCD
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...