74 search results - page 1 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
ENGL
2007
13 years 5 months ago
2007
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
CEC
2005
IEEE
13 years 10 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
VTS
2008
IEEE
13 years 11 months ago
2008
IEEE
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...