Sciweavers

43 search results - page 2 / 9
» Reporting of standard cell placement results
Sort
View
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
ISPD
2003
ACM
105views Hardware» more  ISPD 2003»
13 years 10 months ago
Partition-driven standard cell thermal placement
The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partitio...
Guoqiang Chen, Sachin S. Sapatnekar
DAC
1998
ACM
14 years 5 months ago
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...
Alexander Grießing, Paolo Ienne
VLSID
1996
IEEE
119views VLSI» more  VLSID 1996»
13 years 9 months ago
Parallel simulated annealing strategies for VLSI cell placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
John A. Chandy, Prithviraj Banerjee
ASPDAC
2006
ACM
98views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Timing-driven placement based on monotone cell ordering constraints
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
Chanseok Hwang, Massoud Pedram