60 search results - page 3 / 12 » Retiming with Interconnect and Gate Delay |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
ASPDAC
2009
ACM
13 years 12 months ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...