34 search results - page 2 / 7 » Reusing Scan Chains for Test Pattern Decompression |
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
DFT
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
DELTA
2008
IEEE
14 years 6 days ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...