55 search results - page 1 / 11 » Run-time compaction of FPGA designs |
ERSA
2008
13 years 6 months ago
2008
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
JRoute is a set of Java classes that provide an application programming interface (API) for routing of Xilinx FPGA devices. The interface allows various levels of control from conn...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
CSREAESA
2006
13 years 6 months ago
2006
Traditional simulation-based energy estimation is not practical because the simulation time has increased from minutes and hours and weeks. Therefore, simulation assisted by speci...