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ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 8 months ago
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
Hao Fang, Chenguang Tong, Xu Cheng
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 1 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...
ET
2002
111views more  ET 2002»
13 years 4 months ago
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wun...
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
13 years 8 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
ET
2002
72views more  ET 2002»
13 years 4 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
Abhijit Jas, Nur A. Touba