173 search results - page 2 / 35 » Scan Architecture With Align-Encode |
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...