35 search results - page 3 / 7 » Scan Test Planning for Power Reduction |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
DATE
2009
IEEE
13 years 9 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
TVLSI
2010
13 years 15 days ago
2010