18 search results - page 2 / 4 » Scan Test of IP Cores in an ATE Environment |
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
DFT
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
TVLSI
2008
13 years 5 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...