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» Scheduling and Binding Algorithms for High-Level Synthesis
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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 1 months ago
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
Ansgar Stammermann, Domenik Helms, Milan Schulte, ...
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
13 years 11 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
DAC
1999
ACM
14 years 5 months ago
Soft Scheduling in High Level Synthesis
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
Jianwen Zhu, Daniel Gajski
VLSID
1994
IEEE
124views VLSI» more  VLSID 1994»
13 years 9 months ago
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
Samit Chaudhuri, Robert A. Walker
ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
13 years 9 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi