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» Selective Hardening of NanoPLA Circuits
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DFT
2008
IEEE
82views VLSI» more  DFT 2008»
13 years 11 months ago
Selective Hardening of NanoPLA Circuits
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising...
Ilia Polian, Wenjing Rao
ICCD
2008
IEEE
157views Hardware» more  ICCD 2008»
14 years 1 months ago
Power-aware soft error hardening via selective voltage scaling
—Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking...
Kai-Chiang Wu, Diana Marculescu
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
13 years 11 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
13 years 11 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
13 years 11 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu