Selective Hardening of NanoPLA Circuits

Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising class of nanoelectronic circuits, called NanoPLAs, against errors. An analytical procedure and simulations are both incorporated into the algorithm to identify the most critical error locations. By targeting errors with the largest impact for a given circuit, the method can provide significant reliability boost at low cost. Furthermore, the method yields a plethora of alternative designs, trading off hardening costs against circuit robustness. In many cases, solutions found achieve both lower cost and higher robustness compared with the duplicationbased hardening strategy introduced before.

• Type: Conference
• Year: 2008
• Where: DFT
• Authors: Ilia Polian, Wenjing Rao
• Keywords: Critical Error Locations, DFT 2008, Duplicationbased Hardening Strategy, Hardware, Significant Reliability Boost